F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public

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2.3. Programmed Input/Output Design Example Simulation Testbench

The simulation testbench instantiates the PIO design example and a Root Port BFM to interface with the target Endpoint.

Figure 7. Block Diagram for the PCIe x16 PIO Design Example Simulation Testbench
Figure 8. Block Diagram for the PCIe x8x8 PIO Design Example Simulation Testbench
Note: The simulation testbench for PCIe x8x8 PIO Design Example is configured for a single PCIe x8 link although the actual design implements two PCIe x8 links.
Figure 9. Block Diagram for the PCIe x8 PIO Design Example Simulation Testbench

The test program writes to and reads back data from the same location in the on-chip memory. It compares the data read to the expected result. The test reports, "Simulation stopped due to successful completion" if no errors occur.