F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 12/17/2021
Public

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3.6.1. Running the PIO Design Example

Note: The instructions below are applicable to the F-Tile Avalon Streaming IP for PCI Express Design Example target on a custom board. Intel F-Tile development boards may be supported in a future Intel® Quartus® Prime release.
  1. Navigate to ./software/user/example under the design example directory.
  2. Compile the design example application: $ make
  3. Run the test: $ sudo ./intel_fpga_pcie_link_test

    You can run the Intel FPGA IP PCIe link test in manual or automatic mode. Choose from:
    • In automatic mode, the application automatically selects the device. The test selects the Intel PCIe device with the lowest BDF by matching the Vendor ID. The test also selects the lowest available BAR.
    • In manual mode, the test queries you for the bus, device, and function number and BAR.
    For the Intel Agilex Development Kit, you can determine the BDF by typing the following command:
    $ lspci -d 1172
  4. Here are sample transcripts for automatic and manual modes.
    Figure 23. Automatic Mode
    Figure 24. Manual Mode