PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

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ID 683459
Date 1/23/2017
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences A. Document Revision History
3. Interface and Signal Differences x
3.1. Reset Interfaces 3.2. Serial Interface 3.3. Read DMA Interface 3.4. Write DMA Interface 3.5. Avalon-MM Slave Interfaces 3.6. Avalon-MM Master Interfaces 3.7. Control and Status Register Interface 3.8. Hard IP Reconfiguration Interface 3.9. Interrupt Interface 3.10. Error Interface 3.11. Status and Link Training Interface 3.12. PHY Interface for PCI Express (PIPE) Interface 3.13. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
A. Document Revision History

3.6. Avalon-MM Master Interfaces

Table 7.  Avalon-MM Master Interfaces
Stratix 10 Arria 10, Stratix V Comments

rxm_bar_*

Rxm*

Signal names differ but functionality is the same unless otherwise noted below.

rxm_bar_<m>_writedata_o[<n>-1:0]

rxm_bar_<m>_readdata_o[<n>-1:0]

RxmDataWrite_<m>_o[<n>-1:0]

RxmReadData_<m>_o[<n>-1:0]

<m> is the BAR number, 0-5

<n> is the width of the bus

Stratix 10: All BARs can be bursting, non-bursting, or disabled.<n> has the following values:

  • Non-bursting BAR: <n>=32
  • Bursting BAR: <n>=256

Arria 10, Stratix V: Every BAR can be non-bursting or disabled. For non-bursting BARs <n> = 32.

Only BAR2 supports bursting. If BAR2 is bursting <n>=128 for a 128-bit Avalon-MM interface. <n>=256 for a 256-bit Avalon-MM interface.

rxm_bar_<m>_byteenable_o[<n>-1:0]

RxmByteEnable_<m>_o[<n>-1:0]

<m> is the BAR number, 0-5.

<n> is the width of the bus.

Stratix 10: All BARs can be bursting, non-bursting, or disabled. <n> has the following values:

  • Non-bursting BAR: <n>=4
  • Bursting BAR: <n>=32

Arria 10, Stratix V: Every BAR can be non-bursting or disabled. For non-bursting BARs <n> = 4.

BAR2 only supports bursting. If BAR2 is bursting <n>=16 for a 128-bit Avalon-MM interface. <n>=32 for a 256-bit Avalon-MM interface.

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