PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

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ID 683459
Date 1/23/2017
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences A. Document Revision History
3. Interface and Signal Differences x
3.1. Reset Interfaces 3.2. Serial Interface 3.3. Read DMA Interface 3.4. Write DMA Interface 3.5. Avalon-MM Slave Interfaces 3.6. Avalon-MM Master Interfaces 3.7. Control and Status Register Interface 3.8. Hard IP Reconfiguration Interface 3.9. Interrupt Interface 3.10. Error Interface 3.11. Status and Link Training Interface 3.12. PHY Interface for PCI Express (PIPE) Interface 3.13. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
A. Document Revision History

3.11. Status and Link Training Interface

Table 12.  Status and Link Training Interface
Stratix 10 Arria 10, Stratix V Comments
ltssmstate[5:0]

ltssmstate[4:0]

Stratix 10: Provides finer granularity and different encoding. For example, L0 is now 0x11 instead of 0x0F. Refer to user guide for complete mapping.

link_up

Not supported

Stratix 10: Adds bit for x16 configuration.

Not supported

ev128ns

ev1us

hotrst_exit

l2_exit

dl_up

Stratix 10: Not supported

Arria 10, Stratix V: Refer to the Arria 10 PCIe user guides for more information.

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