PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

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ID 683459
Date 1/23/2017
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences A. Document Revision History
3. Interface and Signal Differences x
3.1. Reset Interfaces 3.2. Serial Interface 3.3. Read DMA Interface 3.4. Write DMA Interface 3.5. Avalon-MM Slave Interfaces 3.6. Avalon-MM Master Interfaces 3.7. Control and Status Register Interface 3.8. Hard IP Reconfiguration Interface 3.9. Interrupt Interface 3.10. Error Interface 3.11. Status and Link Training Interface 3.12. PHY Interface for PCI Express (PIPE) Interface 3.13. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
A. Document Revision History

2. Configuration Options

The parameters available to configure the PCI Express IP core in Stratix 10 devices differ from those available for Stratix V and Arria 10 devices. The following table describes the differences.
Table 1.  Comparison of Stratix 10 and Stratix V or Arria 10 Parameters
Feature Stratix 10 Stratix V or Arria 10 Comments
Supported Link Widths

1,2,4,8,16

1,2,4,8
Interface widths 256 bits only

Avalon-MM: 64 or 128 bits

Avalon-MM with DMA:128 or 256 bits

Stratix 10: Qsys automatically inserts width adaptation logic to interface to the user application.

Port type Native Endpoint

Avalon-MM: Native Endpoint, Root Port

Avalon-MM with DMA: Native Endpoint

Stratix 10 will support Root Ports in a future release.
Number of Avalon-MM slave interfaces supported

Supports the following 2 Avalon-MM TX slave interfaces for either Avalon-MM or Avalon-MM with DMA:

  • 256-bit high performance, bursting TX slave
  • 32-bit non-bursting TX slave

Supports a single Avalon-MM TX slave interface. Supported interfaces differ for Avalon-MM and Avalon-MM with DMA variants as follows:

  • Avalon-MM: 64-or 128-bit bursting interface
  • Avalon-MM with DMA: 32-bit non-bursting interface
Avalon-MM and DMA support The Application interface type parameter on the System Settings tab specifies Avalon-MM interface. The additional Enable Avalon-MM DMA parameter on the Avalon-MM Settings tab turns on the DMA capability. The Application interface type parameter on the System Settings tab selects between Avalon-MM and Avalon-MM with DMA DMA interfaces.

Stratix 10: Up to 2 Avalon-MM interfaces with 1 implementing DMA.

Arria 10, Stratix V: 1 Avalon-MM interface with or without DMA.

Interrupts The Export interrupt conduit interfaces parameter on the Avalon-MM Settings tab exports interrupt interfaces. The Export MSI/MSI-X conduit interfaces parameter on the Avalon-MM Settings tab exports interrupt interfaces. Both parameters export MSI, MSI-X, and legacy interrupt interfaces.
Avalon-MM non-bursting slave interface The Enable non-bursting Avalon-MM Slave interface with individual byte access (TXS) parameter on the Avalon-MM Settings tab controls Avalon-MM TX bursting slave support. Non-bursting Avalon-MM TX slave port is always enabled.

Stratix 10: If DMA is enabled, the 32-bit non-bursting Avalon-MM slave interface must also be enabled.

Arria 10, Stratix V: TX Avalon-MM slave port is always enabled.

Avalon-MM bursting interfaces Bursting is available for all BARs. The Enable burst capability for Avalon-MM BAR<n> Master port on the Base Address Register tab turns on bursting.

When the Application interface type specifies the Avalon-MM with DMA interface, you can turn on Enable burst capability for RXM BAR2 port on the Avalon-MM Settings tab.

Arria 10, Stratix V: If BAR2 is 32-bits and burst capable, BAR3 is not available for other uses. If BAR2 is 64-bits and burst capable, BAR3 drives the upper 32 bits.

Tag support 256 tags.

32 tags.

When the Application Interface Type is Avalon-MM with DMA, the Settings tab includes Enable 256 tags to enable additional tabs.

  • For the Avalon-MM DMA interface, turning on Enable 256 tags improves the performance of high latency systems. This option turns on the Extended Tag bit in the PCI Express Device Capabilities Configuration Space register.
High performance Avalon-MM slave interface (HPTXS) The Enable High Performance bursting Avalon-MM Slave interface (HPTXS) parameter on the Avalon-MM Settings tab turns this port on. Not available.

Arria 10, Stratix V: No separate high performance Avalon-MM TX slave interface.

Address translation table size for high performance TX slave 2, 4, 8, 16, 32, 64, 128, 256, and 512 entries supported. Separate high performance TX slave is not available.  
Error settings By default, Advanced Error Reporting (AER), ECRC Checking, and ECRC Generation are on. You can turn off the AER capability in the Advanced Error Reporting Extended Capability register. You can turn off ECRC generation and checking in the Advanced Error Capabilities and Control register. The parameter editor does not provide controls for these settings. You can configure the following error settings in the parameter editor. By default, they are all turned off.
  • AER
  • ECRC Generation
  • ECRC Checking
  
CvP Not supported in the current release. The Configuration, Debug, and Extensions Options tab includes the Enable Configuration via Protocol (CvP) parameter. Stratix 10: CvP will be supported in a future release.
Hard reset controller Supports hard reset controller only.

Arria 10: supports hard reset controller only.

Stratix V: hard reset controller for Gen1. Soft reset controller for Gen2 and Gen3.

 
Design examples Dynamically generated design example includes the parameters you specify.

Arria 10: Dynamically generated design example includes the parameters you specify.

Stratix V: Static design examples are available in the installation directory.

 
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