PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

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ID 683459
Date 1/23/2017
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences A. Document Revision History
3. Interface and Signal Differences x
3.1. Reset Interfaces 3.2. Serial Interface 3.3. Read DMA Interface 3.4. Write DMA Interface 3.5. Avalon-MM Slave Interfaces 3.6. Avalon-MM Master Interfaces 3.7. Control and Status Register Interface 3.8. Hard IP Reconfiguration Interface 3.9. Interrupt Interface 3.10. Error Interface 3.11. Status and Link Training Interface 3.12. PHY Interface for PCI Express (PIPE) Interface 3.13. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
A. Document Revision History

3.9. Interrupt Interface

Table 10.  Interrupt Interface
Stratix 10 Arria 10, Stratix V Comments

Not available

app_int_ack

Stratix 10: No ACK generated for legacy interrupts. User logic must form and parse packets.

int_status[7:0]

int_status[3:0]

Stratix 10: Supports legacy interrupts A, B, C, and D. Supports the following 4 additional status signals:

  • [4]: RC AER error interrupt status
  • [5]: Root complex PME interrupt status
  • [6]: Asserted when hot plug event occurs and PME is enabled
  • [7]: Hot plug event interrupt status

Arria 10, Stratix V: Supports Legacy Interrupts A, B, C, and D.

int_status_common[2:0]

Not supported

Stratix 10: Supports the following 4 status indicators:

  • [0]: Interrupt status for autonomous bandwidth status register

  • [1]: Interrupt status for bandwidth management status register

  • [2]: Interrupt status for link equalization request bit in the link status register
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