PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

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ID 683459
Date 1/23/2017
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences A. Document Revision History
3. Interface and Signal Differences x
3.1. Reset Interfaces 3.2. Serial Interface 3.3. Read DMA Interface 3.4. Write DMA Interface 3.5. Avalon-MM Slave Interfaces 3.6. Avalon-MM Master Interfaces 3.7. Control and Status Register Interface 3.8. Hard IP Reconfiguration Interface 3.9. Interrupt Interface 3.10. Error Interface 3.11. Status and Link Training Interface 3.12. PHY Interface for PCI Express (PIPE) Interface 3.13. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
A. Document Revision History

3.13. Test Interface

Table 14.  Test Interface
Stratix 10 Arria 10, Stratix V Comments

test_in[66:0]

aux_test_out[6:0]

test_out[255:0]

test_in[63:0]

Stratix 10:
  • test_out[255:0]: available only in x16 configuration
  • aux_test_out[6:0]: available in x8 or smaller configurations
Level Two Title