PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

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ID 683459
Date 1/23/2017
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences A. Document Revision History
3. Interface and Signal Differences x
3.1. Reset Interfaces 3.2. Serial Interface 3.3. Read DMA Interface 3.4. Write DMA Interface 3.5. Avalon-MM Slave Interfaces 3.6. Avalon-MM Master Interfaces 3.7. Control and Status Register Interface 3.8. Hard IP Reconfiguration Interface 3.9. Interrupt Interface 3.10. Error Interface 3.11. Status and Link Training Interface 3.12. PHY Interface for PCI Express (PIPE) Interface 3.13. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
A. Document Revision History

3.3. Read DMA Interface

Table 4.  Read DMA Interface
Stratix 10 Arria 10, Stratix V Comments

rd_dma_*

RdDMA*

Signal names differ, but functionality is the same unless otherwise noted below.

rd_dma_write_data_o[255:0]

RdDmaWriteData_o[<n-1>:0]

Stratix 10: Supports 256-bit interface only.

Arria 10, Stratix V: <n> = 128 or 256

rd_dts_*

RdDTS* Signal names differ for descriptor table slave interface, but functionality is the same unless otherwise noted below.
rd_dts_write_data_i[255:0] RdDTSWriteData_i[<n-1>:0]

Stratix 10: Supports 256-bit interface only.

Arria 10, Stratix V:

<n> = 128 or 256

rd_dts_burst_count_i[4:0] RdDTSBurstCount_i[<n-1>:0]

Stratix 10: Supports 256-bit bit interface only.

Arria 10, Stratix V:

<n> = 5 for a 256-bit interface.

<n> = 6 for a 128-bit interface.

rd_dcm_* RdDCM* Signal names differ but functionality is the same.
rd_ast_rx* RdAstRx* Signal names differ but functionality is the same.
rd_ast_tx* RdAstTx* Signal names differ but functionality is the same.
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