PCI Express: Migrating to Stratix 10 from Arria 10 for the Avalon-MM and Avalon-MM DMA Interfaces

Download PDF
ID 683459
Date 1/23/2017
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences A. Document Revision History
3. Interface and Signal Differences x
3.1. Reset Interfaces 3.2. Serial Interface 3.3. Read DMA Interface 3.4. Write DMA Interface 3.5. Avalon-MM Slave Interfaces 3.6. Avalon-MM Master Interfaces 3.7. Control and Status Register Interface 3.8. Hard IP Reconfiguration Interface 3.9. Interrupt Interface 3.10. Error Interface 3.11. Status and Link Training Interface 3.12. PHY Interface for PCI Express (PIPE) Interface 3.13. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
A. Document Revision History

3.10. Error Interface

Table 11.  Error Interface
Stratix 10 Arria 10, Stratix V Comments

tx_par_err

tx_par_err[1:0]

Stratix 10: The TX Transaction Layer or TX Data Link Layer asserts tx_par_err to indicate a parity error.

Arria 10, Stratix V: The following encodings are defined:

  • 2’b10: TX Transaction Layer detects a parity error

    2’b01: TX Data Link Layer detects a parity error

derr_uncor_ext_rcv

Not supported

Stratix 10: When asserted, indicates an uncorrectable 2-bit ECC error in the RX buffer.

Arria 10, Stratix V: Not supported.

Not supported

cfg_par_err

Stratix 10: Not supported.

Arria 10, Stratix V: Indicates a parity error in a TLP routed to the internal Configuration Space. This error is also logged in the Vendor Specific Extended Capability Internal Error register. You must reset the IP core if this error occurs.

Level Two Title