Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Document Revision History for Cyclone® V Device Datasheet

Document Version Changes
2023.05.23 Updated the absolute VMAX for a receiver pin specifications in the Receiver Specifications for Cyclone® V GX, GT, SX, and ST Devices table.
2019.11.27
  • Updated tCO parameter in the AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone® V Devices (For Non Cyclone® V QS Packages) table.
  • Added active serial (AS) configuration timing for Cyclone® V QS package.
  • Added a note to indicate that the specifications are not applicable to Cyclone® V QS package in the following tables:
    • DCLK-to-DATA[] Ratio for Cyclone® V Devices
    • FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone® V Devices
    • FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone® V Devices
    • PS Timing Parameters for Cyclone® V Devices
  • Added a note to indicate that the specifications are applicable to both Cyclone® V QS and non QS packages in the DCLK Frequency Specification in the AS Configuration Scheme table.
2019.01.25
  • Changed "VCO post-scale counter K value" to "VCO post divider value" in the fVCO note in the PLL Specifications for Cyclone® V Devices table.
  • Updated the AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone® V Devices table.
    • Updated tDH specifications. These specifications are applicable to the commercial, industrial, and automotive grade devices.
    • Added note to tCO and tSU.
2018.05.07
  • Added description about the low-power option ("L" suffix) for Cyclone® V SE and SX devices.
  • Added the Cyclone® V Devices Overshoot Duration diagram.
  • Removed the description on SD/MMC interface calibration support in the Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone® V Devices table. This feature is currently supported in the preloader.
  • Removed the note to Cyclone® V SE A2 and A4 devices, and Cyclone® V SX C2 and C4 devices in the Uncompressed .rbf Sizes for Cyclone® V Devices table. These devices are currently supported in the Intel® Quartus® Prime software.
  • Removed PowerPlay text from tool name.
  • Updated the IP name from ALTREMOTE_UPDATE to Remote Update Intel FPGA IP.
  • Rebranded as Intel.
  • Added the Low Power Variants table and the estimating power consumption steps to the " Cyclone® V Device Datasheet" Overview section.
  • Updated the minimum value for tDH to 2.5 for -6 speed grade/2.9 for -7 and -8 speed grade.
Date Version Changes
December 2016 2016.12.09
  • Updated VICM (AC coupled) specifications for 1.5 V PCML in Receiver Specifications for Cyclone® V GX, GT, SX, and ST Devices table.
  • Added maximum specification for Td in Management Data Input/Output (MDIO) Timing Requirements for Cyclone® V Devices table.
  • Updated Tinit specifications in the following tables:
    • FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone® V Devices
    • FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone® V Devices
    • AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone® V Devices
    • PS Timing Parameters for Cyclone® V Devices
June 2016 2016.06.10
  • Changed pin capacitance to maximum values.
  • Updated SPI Master Timing Requirements for Cyclone® V Devices table.
    • Added Tsu and Th specifications.
    • Removed Tdinmax specifications.
  • Updated SPI Master Timing Diagram.
  • Updated Tclk spec from maximum to minimum in I2C Timing Requirements for Cyclone® V Devices table.
December 2015 2015.12.04
  • Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone® V Devices table.
    • Updated Fclk, Tdutycycle, and Tdssfrst specifications.
    • Added Tqspi_clk, Tdin_start, and Tdin_end specifications.
    • Removed Tdinmax specifications.
  • Updated the minimum specification for Tclk to 16.67 ns and removed the maximum specification in SPI Master Timing Requirements for Cyclone® V Devices table.
  • Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone® V Devices table.
    • Updated T clk to Tsdmmc_clk_out symbol.
    • Updated Tsdmmc_clk_out and Td specifications.
    • Added Tsdmmc_clk, Tsu, and Th specifications.
    • Removed Tdinmax specifications.
  • Updated the following diagrams:
    • Quad SPI Flash Timing Diagram
    • SD/MMC Timing Diagram
  • Updated configuration .rbf sizes for Cyclone® V devices.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.12
  • Updated the supported data rates for the following output standards using true LVDS output buffer types in the High-Speed I/O Specifications for Cyclone® V Devices table:
    • True RSDS output standard: data rates of up to 360 Mbps
    • True mini-LVDS output standard: data rates of up to 400 Mbps
  • Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash.
  • Updated Th location in I2C Timing Diagram.
  • Updated Twp location in NAND Address Latch Timing Diagram.
  • Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone® V Devices table.
  • Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Cyclone® V Devices chapter.
    • FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1
    • FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1
    • AS Configuration Timing Waveform
    • PS Configuration Timing Waveform
March 2015 2015.03.31
  • Added VCC specifications for devices with internal scrubbing feature (with SC suffix) in Recommended Operating Conditions table.
  • Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone® V Devices table.
January 2015 2015.01.23
  • Updated the transceiver specification for Cyclone® V ST from 5 Gbps to 6.144 Gbps. Updated the note in the following tables:
    • Transceiver Power Supply Operating Conditions for Cyclone® V GX, GT, SX, and ST Devices
    • Transceiver Specifications for Cyclone® V GX, GT, SX, and ST Devices
    • Transceiver Compliance Specification for All Supported Protocol for Cyclone® V Devices
  • Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply”. Added a note to state that VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone® V SX C5, C6, D5, and D6 devices, and Cyclone® V SE A5 and A6 devices. Updated in the following tables:
    • Absolute Maximum Ratings for Cyclone® V Devices
    • HPS Power Supply Operating Conditions for Cyclone® V SE, SX, and ST Devices
  • Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
  • Updated the conditions for transceiver reference clock rise time and fall time: Measure at ±60 mV of differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK phase noise specification.
  • Updated fVCO maximum value from 1400 MHz to 1600 MHz for –C7 and –I7 speed grades in the PLL specifications table.
  • Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design.
  • Added the following notes in the High-Speed I/O Specifications for Cyclone® V Devices table:
    • The Cyclone® V devices support true RSDS output standard with data rates of up to 230 Mbps using true LVDS output buffer types on all I/O banks.
    • The Cyclone® V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using true LVDS output buffer types on all I/O banks.
  • Updated HPS Clock Performance main_base_clk specifications from 462 MHz to 400 MHz for –C6 speed grade.
  • Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C7, –I7, –A7, and –C8 speed grades) and 1,850 MHz (for –C6 speed grade).
  • Changed the symbol for HPS PLL input jitter divide value from NR to N.
  • Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables:
    • SPI Master Timing Requirements for Cyclone® V Devices
    • SPI Slave Timing Requirements for Cyclone® V Devices
  • Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board.
  • Added HPS JTAG timing specifications.
  • Updated the configuration .rbf size (bits) for Cyclone® V devices.
  • Added a note to Uncompressed .rbf Sizes for Cyclone® V Devices table: The recommended EPCQ serial configuration devices are able to store more than one image.
July 2014 3.9
  • Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
  • Added a note in Table 19: Differential inputs are powered by VCCPD which requires 2.5 V.
  • Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20.
  • Updated h2f_user2_clk specification for –C6, –C7, and –I7 speed grades in Table 34.
  • Updated description in “HPS PLL Specifications” section.
  • Updated VCO range maximum specification in Table 35.
  • Updated Td and Th specifications in Table 41.
  • Added Th specification in Table 43 and Figure 10.
  • Updated a note in Figure 17, Figure 18, and Figure 20 as follows: Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required.
  • Removed “Remote update only in AS mode” specification in Table 54.
  • Added DCLK device initialization clock source specification in Table 56.
  • Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for the Configuration via Protocol (CvP) feature.
  • Added "Recommended EPCQ Serial Configuration Device" values in Table 57.
  • Removed fMAX_RU_CLK specification in Table 59.
February 2014 3.8
  • Updated VCCRSTCLK_HPS maximum specification in Table 1.
  • Added VCC_AUX_SHARED specification in Table 1.
December 2013 3.7
  • Updated Table 1, Table 3, Table 19, Table 20, Table 23, Table 25, Table 27, Table 34, Table 44, Table 51, Table 52, Table 55, and Table 61.
  • Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 24, Table 25, Table 26, Table 27, Table 28, Table 32, Table 33, Table 49, Table 50, Table 51, Table 52, Table 53, Table 54, Table 55, Table 57, Table 58, Table 59, Table 60, and Table 62.
November 2013 3.6 Updated Table 23, Table 30, and Table 31.
October 2013 3.5
  • Added “HPS PLL Specifications”.
  • Added Table 23, Table 35, and Table 36.
  • Updated Table 1, Table 5, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, Table 28, Table 34, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, and Table 53.
  • Updated Figure 1, Figure 2, Figure 4, Figure 10, Figure 12, Figure 13, and Figure 16.
  • Removed table: GPIO Pulse Width for Cyclone® V Devices.
June 2013 3.4
  • Updated Table 20, Table 27, and Table 34.
  • Updated “UART Interface” and “CAN Interface” sections.
  • Removed the following tables:
    • Table 45: UART Baud Rate for Cyclone® V Devices
    • Table 47: CAN Pulse Width for Cyclone® V Devices
May 2013 3.3
  • Added Table 33.
  • Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20.
  • Updated Table 1, Table 4, Table 5, Table 10, Table 13, Table 19, Table 20, Table 26, Table 32, Table 35, Table 36, Table 43, Table 53, Table 54, Table 57, and Table 61.
March 2013 3.2
  • Added HPS reset information in the “HPS Specifications” section.
  • Added Table 57.
  • Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56.
  • Updated Figure 18.
January 2013 3.1 Updated Table 4, Table 20, and Table 56.
November 2012 3.0
  • Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19, Table 20, Table 25, Table 28, Table 52, Table 55, Table 56, and Table 59.
  • Removed table: Transceiver Block Jitter Specifications for Cyclone® V GX Devices.
  • Added HPS information:
    • Added “HPS Specifications” section.
    • Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, and Table 46.
    • Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, and Figure 16.
    • Updated Table 3.
June 2012 2.0 Updated for the Quartus® Prime software v12.0 release:
  • Restructured document.
  • Removed “Power Consumption” section.
  • Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30, Table 31, Table 34, Table 36, Table 37, Table 38, Table 39, Table 41, Table 43, and Table 46.
  • Added Table 22, Table 23, and Table 29.
  • Added Figure 1 and Figure 2.
  • Added “Initialization” and “Configuration Files” sections.
February 2012 1.2
  • Added automotive speed grade information.
  • Added Figure 2–1.
  • Updated Table 2–3, Table 2–8, Table 2–9, Table 2–19, Table 2–20, Table 2–21, Table 2–22, Table 2–23, Table 2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28, Table 2–30, Table 2–35, and Table 2–43.
  • Minor text edits.
November 2011 1.1
  • Added Table 2–5.
  • Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21.
October 2011 1.0 Initial release.
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