Cyclone V Device Datasheet

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ID 683801
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Datasheet
Cyclone V Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for Cyclone® V Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications OCT Variation after Power-Up Calibration Pin Capacitance Hot Socketing Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Differential HSTL and HSUL I/O Standards Differential I/O Standard Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance HPS Specifications
Transceiver Performance Specifications x
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Typical TX VOD Setting for Cyclone® V Transceiver Channels with termination of 100 Ω Transmitter Pre-Emphasis Levels Transceiver Compliance Specification
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Performance Specifications Memory Block Performance Specifications
Periphery Performance x
High-Speed I/O Specifications DLL Frequency Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications Duty Cycle Distortion (DCD) Specifications
HPS Specifications x
HPS Clock Performance HPS PLL Specifications Quad SPI Flash Timing Characteristics SPI Timing Characteristics SD/MMC Timing Characteristics USB Timing Characteristics Ethernet Media Access Controller (EMAC) Timing Characteristics I2C Timing Characteristics NAND Timing Characteristics Arm* Trace Timing Characteristics UART Interface GPIO Interface CAN Interface HPS JTAG Timing Specifications
HPS PLL Specifications x
HPS PLL VCO Frequency Range HPS PLL Input Clock Range HPS PLL Input Jitter
Configuration Specifications x
POR Specifications FPGA JTAG Configuration Timing FPP Configuration Timing Active Serial (AS) Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme Passive Serial (PS) Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Oscillator Frequency Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
I/O Timing x
Programmable IOE Delay Programmable Output Buffer Delay
Cyclone V Device Datasheet

Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices

Table 21.  Reference Clock Specifications for Cyclone® V GX, GT, SX, and ST Devices
Symbol/Description Condition Transceiver Speed Grade 5 30 Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit
Min Typ Max Min Typ Max Min Typ Max
Supported I/O standards 1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL31, HCSL, and LVDS
Input frequency from REFCLK input pins32 — 27 — 550 27 — 550 27 — 550 MHz
Rise time Measure at ±60 mV of differential signal 33 — — 400 — — 400 — — 400 ps
Fall time Measure at ±60 mV of differential signal33 — — 400 — — 400 — — 400 ps
Duty cycle — 45 — 55 45 — 55 45 — 55 %
Peak-to-peak differential input voltage — 200 — 2000 200 — 2000 200 — 2000 mV
Spread-spectrum modulating clock frequency PCIe* 30 — 33 30 — 33 30 — 33 kHz
Spread-spectrum downspread PCIe* — 0 to –0.5% — — 0 to –0.5% — — 0 to –0.5% — —
On-chip termination resistors — — 100 — — 100 — — 100 — Ω
VICM (AC coupled) — VCCE_GXBL supply 34 35 VCCE_GXBL supply VCCE_GXBL supply V
VICM (DC coupled) HCSL I/O standard for the PCIe* reference clock 250 — 550 250 — 550 250 — 550 mV
Transmitter REFCLK phase noise36 10 Hz — — –50 — — –50 — — –50 dBc/Hz
100 Hz — — –80 — — –80 — — –80 dBc/Hz
1 KHz — — –110 — — –110 — — –110 dBc/Hz
10 KHz — — –120 — — –120 — — –120 dBc/Hz
100 KHz — — –120 — — –120 — — –120 dBc/Hz
≥1 MHz — — –130 — — –130 — — –130 dBc/Hz
RREF — — 2000 ±1% — — 2000 ±1% — — 2000 ±1% — Ω
Table 22.  Transceiver Clocks Specifications for Cyclone® V GX, GT, SX, and ST Devices
Symbol/Description Condition Transceiver Speed Grade 530 Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit
Min Typ Max Min Typ Max Min Typ Max
fixedclk clock frequency PCIe* Receiver Detect — 125 — — 125 — — 125 — MHz
Transceiver Reconfiguration Controller IP (mgmt_clk_clk) clock frequency — 75 — 100/125 37 75 — 100/12537 75 — 100/12537 MHz
Table 23.  Receiver Specifications for Cyclone® V GX, GT, SX, and ST Devices
Symbol/Description Condition Transceiver Speed Grade 530 Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit
Min Typ Max Min Typ Max Min Typ Max
Supported I/O standards 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate38 — 614 — 5000/614435 614 — 3125 614 — 2500 Mbps
Absolute VMAX for a receiver pin39 — — — 1.35 — — 1.35 — — 1.35 V
Absolute VMIN for a receiver pin — –0.4 — — –0.4 — — –0.4 — — V
Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration — — — 1.6 — — 1.6 — — 1.6 V
Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration — — — 2.2 — — 2.2 — — 2.2 V
Minimum differential eye opening at the receiver serial input pins40 — 110 — — 110 — — 110 — — mV
Differential on-chip termination resistors 85-Ω setting — 85 — — 85 — — 85 — Ω
100-Ω setting — 100 — — 100 — — 100 — Ω
120-Ω setting — 120 — — 120 — — 120 — Ω
150-Ω setting — 150 — — 150 — — 150 — Ω
VICM (AC coupled) 2.5 V PCML, LVPECL, and LVDS VCCE_GXBL supply34 35 VCCE_GXBL supply VCCE_GXBL supply V
1.5 V PCML 0.65/0.75/0.8 41 V
tLTR 42 — — — 10 — — 10 — — 10 µs
tLTD 43 — — — 4 — — 4 — — 4 µs
tLTD_manual 44 — — — 4 — — 4 — — 4 µs
tLTR_LTD_manual 45 — 15 — — 15 — — 15 — — µs
Programmable ppm detector46 — ±62.5, 100, 125, 200, 250, 300, 500, and 1000 ppm
Run length — — — 200 — — 200 — — 200 UI
Programmable equalization AC and DC gain

AC gain setting = 0 to 3 47

DC gain setting = 0 to 1

Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone® V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone® V GX, GT, SX, and ST Devices diagrams. dB
Table 24.  Transmitter Specifications for Cyclone® V GX, GT, SX, and ST Devices
Symbol/Description Condition Transceiver Speed Grade 530 Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit
Min Typ Max Min Typ Max Min Typ Max
Supported I/O standards 1.5 V PCML
Data rate — 614 — 5000/614435 614 — 3125 614 — 2500 Mbps
VOCM (AC coupled) — — 650 — — 650 — — 650 — mV
Differential on-chip termination resistors 85-Ω setting — 85 — — 85 — — 85 — Ω
100-Ω setting — 100 — — 100 — — 100 — Ω
120-Ω setting — 120 — — 120 — — 120 — Ω
150-Ω setting — 150 — — 150 — — 150 — Ω
Intra-differential pair skew TX VCM = 0.65 V and slew rate of 15 ps — — 15 — — 15 — — 15 ps
Intra-transceiver block transmitter channel-to-channel skew ×6 PMA bonded mode — — 180 — — 180 — — 180 ps
Inter-transceiver block transmitter channel-to-channel skew ×N PMA bonded mode — — 500 — — 500 — — 500 ps
Table 25.  CMU PLL Specifications for Cyclone® V GX, GT, SX, and ST Devices
Symbol/Description Condition Transceiver Speed Grade 530 Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit
Min Typ Max Min Typ Max Min Typ Max
Supported data range — 614 — 5000/614435 614 — 3125 614 — 2500 Mbps
fPLL supported data range — 614 — 3125 614 — 3125 614 — 2500 Mbps
Table 26.  Transceiver-FPGA Fabric Interface Specifications for Cyclone® V GX, GT, SX, and ST Devices
Symbol/Description Condition Transceiver Speed Grade 530 Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit
Min Typ Max Min Typ Max Min Typ Max
Interface speed (single-width mode) — 25 — 187.5 25 — 187.5 25 — 163.84 MHz
Interface speed (double-width mode) — 25 — 163.84 25 — 163.84 25 — 156.25 MHz
Related Information
30 Transceiver Speed Grade 5 covers specifications for Cyclone® V GT and ST devices.
31 Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
32 The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information about CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone® V Devices chapter.
33 REFCLK performance requires to meet transmitter REFCLK phase noise specification.
34 Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone® V GT and ST FPGA systems which require full compliance to the PCIe* Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone® V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone® V Devices chapter.
35 Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps ( Cyclone® V GT and ST devices) and 6.144 Gbps ( Cyclone® V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone® V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone® V Devices chapter.
36 The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12.
37 The maximum supported clock frequency is 100 MHz if the PCIe* hard IP block is enabled or 125 MHz if the PCIe* hard IP block is not enabled.
38 To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
39 The device cannot tolerate prolonged operation at this absolute maximum.
40 The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
41 The AC coupled VICM = 650 mV for Cyclone® V GX and SX in PCIe* mode only. The AC coupled VICM = 750mV for Cyclone® V GT and ST in PCIe* mode only.
42 tLTR is the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency after coming out of reset.
43 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
44 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode.
45 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode.
46 The rate matcher supports only up to ±300 parts per million (ppm).
47 The Intel® Quartus® Prime software allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only.
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