Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5.3.1. Downloading and Generating the High Performance Reference Design

Follow these steps to regenerate the PCI Express High Performance Reference Design with CvP enabled:
  1. Download the PCIe AVST and On-Chip Memory Interface design files from the PCI Express Protocol web page. This design includes the correct pin assignments and project settings to target the Stratix V GX FPGA Development Kit.
  2. Unzip PCIe_SVGX_AVST_On_Chip_Mem_140.zip.
  3. Copy hip_s5gx_x1_g1_ast64_140.qar to your working directory.
  4. Start the Quartus Prime software and restore hip_s5gx_x1_g1_ast64_140.qar .
  5. On the Tools menu, select Qsys.
  6. Open top.qsys.
  7. On the System Contents tab, right-click DUT and select Edit.
  8. Under System Settings, turn on Enable configuration via the PCIe link as shown in the following figure.
    Figure 36. Hard IP for PCI Express Parameter Editor
  9. Click Finish.
  10. On the Generation tab, specify the settings in the following table. Then click Generate at the bottom of the window.
    Table 18.  Qsys Generation Tab Settings
    Parameter Value

    Create simulation model

    None

    Create testbench Qsys system

    None

    Create testbench simulation model

    None

    Create HDL design files for synthesis

    Verilog

    Create block symbol file (.bsf)

    Leave this entry off.

    Path

    < working_dir> top

    Simulation

    Leave this entry blank.

    Testbench

    <working_dir> /top /synthesis

    Figure 37. Qsys Generation Window
  11. After successful compilation, close Qsys.
  12. After creating an IP Variation, to add this IP to your Quartus project, you must manually add the .qip and .sip files.
    The .qip is located in <working_dir>/synthesis/top.qip
    The .sip is located in <working_dir>/simulation/top.sip
    Figure 38.  Intel® Quartus® Prime Reminder
  13. On the Assignments menu, select Settings.
  14. In the Files category, remove the existing top.qip IP Variation File.
  15. Browse to the new top.qip file created after generating the IP Core, located in <working_dir>/synthesis/top.qip.
  16. Click Add and OK to close the Settings window.
    Figure 39. Settings Window