Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

6.3.9. Uncorrectable Internal Error Mask Register

This register controls which errors are forwarded as internal uncorrectable errors. With the exception of the configuration errors detected in CvP mode, all of the errors are severe and may place the device or PCIe link in an inconsistent state. The configuration error detected in CvP mode may be correctable depending on the design of the programming software.

Table 35.  Uncorrectable Internal Error Mask Register (Byte Offset: 0x238)
Bits Reset Value Access Description
[31:12] 0x00 RO Reserved.
[11] 1'b1 RWS Mask for RX buffer posted and completion overflow error.
[10] 1'b1 RWS Mask for parity error on the R2CSEB interface.
[9] 1'b1 RWS Mask for parity error on the Configuration Space to TX bus interface.
[8] 1'b1 RWS Mask for parity error on the TX to Configuration Space bus interface.
[7] 1'b1 RWS Mask for parity error in the transaction layer packet.
[6] 1'b1 RWS Mask for parity error in the application layer.
[5] 1'b0 RWS Mask for configuration error in CvP mode.
[4] 1'b1 RWS Mask for data parity errors detected during TX Data Link LCRC generation.
[3] 1'b1 RWS Mask for data parity errors detected on the RX to Configuration Space Bus interface.
[2] 1'b1 RWS Mask for data parity error detected at the input to the RX Buffer.
[1] 1'b1 RWS Mask for the retry buffer uncorrectable ECC error.
[0] 1'b1 RWS Mask for the RX buffer uncorrectable ECC error.