Configuration via Protocol (CvP) Implementation in V-series FPGA Devices User Guide

ID 683889
Date 9/04/2020
Public
Document Table of Contents

5.2.2. Workaround for a Known Issue with Transceiver Reconfiguration Controller IP Core

If you plan to perform almost continuous updates of the reconfigurable core logic in stress tests or in your actual system, you may encounter an issue with the Transceiver Reconfiguration Controller. This issue might cause the PCIe link to downtrain in Quartus II 13.0 release and earlier versions of the Quartus II software. If you are using Quartus II 13.0 SP1 or later versions of the Quartus II software, then you may not encounter this issue. Complete the following steps to avoid this issue:
  1. Open pcie_lib/top.v.
  2. Search for the Reconfiguration Controller instance named alt_xcvr_reconfig and comment out the entire reconfig_controller in top.v. (The Transceiver Reconfiguration Controller instance includes 32 lines of Verilog HDL code. )
  3. Add these 5 lines of Verilog HDL following after the commented out instance alt_xcvr_reconfig:

    wire [69:0] reconfig_to_xcvr_bus = {24'h0, 2'b11, 44'h0};

    assign pcie_reconfig_driver_0_reconfig_mgmt_waitrequest = 1'b0;

    assign pcie_reconfig_driver_0_reconfig_mgmt_readdata = 32'h0;

    assign alt_xcvr_reconfig_0_reconfig_busy_reconfig_busy = 1'b0;

    assign alt_xcvr_reconfig_0_reconfig_to_xcvr_reconfig_to_xcv r = { 2 {reconfig_to_xcvr_bus}};

    In this example, the first statement hardwires the reconfig_to_xcvr_bus to the correct values per channel. The first three assignment statements specify the correct values for the waitrequest, readdata, reconfig_busy signals. The final assignment statement for alt_xcvr_reconfig_0_reconfig_to_xcvr_reconfig_to_xcvr represents the full reconfiguration bus for all active transceiver channels. This bus is replicated 2 times because 2 channels are active in the Gen1 x1 instance.