Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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2.17.1. Adding Assertion Monitors for Simulation

You can add monitors to Avalon® Memory-Mapped, AXI, and Avalon® Streaming interfaces in your system to verify protocol and test coverage with a simulator that supports SystemVerilog assertions.
Note: The Questa* - Intel® FPGA Edition simulator does not support SystemVerilog assertions. If you want to use assertion monitors, you must use a supported third-party simulator. For more information, refer to Introduction to Intel FPGA IP Cores.
Figure 54. Inserting an Avalon® Memory-Mapped Monitor Between an Avalon® Memory-Mapped Host and Agent InterfaceThis example demonstrates the use of a monitor with an Avalon® Memory-Mapped monitor between the pcie_compiler bar1_0_Prefetchable Avalon® Memory-Mapped host interface, and the dma_0 control_port_agent Avalon® Memory-Mapped agent interface.

Similarly, you can insert an Avalon® Streaming monitor between Avalon® Streaming source and sink interfaces.