Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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2.16.4. Files Generated for Platform Designer Systems

The Intel® Quartus® Prime Pro Edition software generates the following output file structure for Platform Designer systems. Platform Designer automatically adds the generated .qsys system file to the open Intel® Quartus® Prime project following generation.
Figure 50. Files generated for Platform Designer Systems
Table 19.  Files Generated for Platform Designer Systems

File Name

Description

<your_system>.qsys

The Platform Designer system.

<your_subsystem>.qsys

The Platform Designer subsystem.

ip/

Contains the parameter files for the IP components in the system and subsystems.
<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you can use in VHDL design files.
<your_system>_generation.rpt IP or Platform Designer generation log file. A summary of the messages during IP generation.
<your_system>.qgsimc

Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL.

<your_system>.qgsynth

Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL.

<your_system>.qip

Contains all the required information about the IP component to integrate and compile the IP component in the Intel® Quartus® Prime software.

<your_system>.csv Contains information about the upgrade status of the IP component.

your_system.bsf

A Block Symbol File (.bsf) representation of the IP variation for use in Block Diagram Files (.bdf).

<your_system<>.spd

Required input file for ip-make-simscript to generate simulation scripts for supported simulators. The .spd file contains a list of files generated for simulation, along with information about memories that you can initialize.

<your_system>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components created for use with the Pin Planner.
<your_system>_bb.v Use the Verilog black box (_bb.v) file as an empty module declaration for use as a black box.
<your_system>.sip Contains information required for NativeLink simulation of IP components. Add the .sip file to your Intel® Quartus® Prime Standard Edition project to enable NativeLink for supported devices. The Intel® Quartus® Prime Pro Edition software does not support NativeLink simulation.
<your_system>_inst.v or _inst.vhd HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<your_system>.regmap If the IP contains register information, the Intel® Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of host and agent interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console.
<your_system>.svd

Allows HPS System Debug tools to view the register maps of peripherals connected to HPS within a Platform Designer system.

During synthesis, the Intel® Quartus® Prime software stores the .svd files for agent interface visible to the System Console hosts in the .sof file in the debug session. System Console reads this section, which Platform Designer can query for register map information. For system agents, Platform Designer can access the registers by name.

<your_system>.v <your_ip>.vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation.
mentor/

Contains a ModelSim* script msim_setup.tcl to set up and run a simulation.

aldec/

Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation.

/synopsys/vcs

/synopsys/vcsmx

Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.

Contains a shell script vcsmx_setup.sh and synopsys_ sim.setup file to set up and run a VCS* MX simulation.

/cadence

Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.

/xcelium

Contains a shell script xcelium_setup.sh and other setup files to set up and run a Xcelium* simulation.

/common

Contains a set of Tcl files, <simulator>_files.tcl, which provide all design related simulation information required by a corresponding simulation script. The Tcl file contains designs from current system-level hierarchy, and references to sub-systems and IP components.

/submodules Contains HDL files for the IP core submodule.
<IP submodule>/ For each generated IP submodule directory, Platform Designer generates /synth and /sim sub-directories.

For generated IP components, Platform Designer appends unique suffixes (hashes) to the IP component’s RTL file name to ensure uniqueness of the RTL file and IP component file. The uniqueness of the files is necessary because a system can have multiple instances of the same IP, each with different parameterizations, resulting in multiple variances of the IP component. The hash derives from the parameterization that you specify for the IP component. This methodology ensures no collisions between the multiple variants of the same IP.