Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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6.6.4.3.1. Reset Sequencer Status Register

The Status register indicates which sources are allowed to cause a reset.

You can clear bits by writing 1 to the bit location. The Reset Sequencer ignores attempts to write bits with a value of 0. If the sequencer is reset (power-on-reset), all bits are cleared, except the power-on-reset bit.

Table 87.  Values for the Status Register at Offset 0x00
Bit Attribute Default Description
31 RO 0 Reset Active—Indicates that the sequencer is currently active in reset sequence (assertion or deassertion).
30 RW1C 0

Reset Asserted and waiting for SW to proceed—Set when there is an active reset assertion, and the next sequence is waiting for the software to proceed.

Only valid when the Enable SW sequenced reset assert option is turned on.

29 RW1C 0 Reset Deasserted and waiting for SW to proceed—Set when there is an active reset deassertion, and the next sequence is waiting for the software to proceed.

Only valid when the Enable SW sequenced reset deassert option is turned on.

28:26 Reserved.
25:16 RW1C 0 Reset deassertion input qualification signal reset_dsrt_qual [9:0] status—Indicates that the reset deassertion's input signal qualification signal is set. This bit is set on the detection of assertion of the signal.
15:12 Reserved.
11 RW1C 0 reset_in9 was triggered—Indicates that reset_in9 triggered the reset. Software clears this bits by writing 1 to this location.
10 RW1C 0 reset_in8 was triggered—Indicates that reset_in8 triggered the reset. Software clears this bit by writing 1 to this location.
9 RW1C 0 reset_in7 was triggered—Indicates that reset_in7 triggered the reset. Software clears this bit by writing 1 to this location.
8 RW1C 0 reset_in6 was triggered—Indicates that reset_in6 triggered the reset. Software clears this bit by writing 1 to this location.
7 RW1C 0 reset_in5 was triggered—Indicates that reset_in5 triggered the reset. Software clears this bit by writing 1 to this location.
6 RW1C 0 reset_in4 was triggered—Indicates that reset_in4 triggered the reset. Software clears this bit by writing 1 to this location.
5 RW1C 0 reset_in3 was triggered—Indicates that reset_in3 triggered the reset. Software clears this bit by writing 1 to this location.
4 RW1C 0 reset_in2 was triggered—Indicates that reset_in2 triggered the reset. Software clears this bit by writing 1 to this location.
3 RW1C 0 reset_in1 was triggered—Indicates that reset_in1 triggered the reset. Software clears this bit by writing 1 to this location.
2 RW1C 0 reset_in0 was triggered—Indicates that reset_in0 triggered. Software clears this bit by writing 1 to this location.
1 RW1C 0 Software-triggered reset—Indicates that the software-triggered reset is set by the software, and triggering a reset.
0 RW1C 0 Power-on-reset was triggered—Asserted whenever the reset to the sequencer is triggered. This bit is NOT reset when sequencer is reset. Software clears this bit by writing 1 to this location.