Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.6.2.3. Avalon® Memory Mapped Burst Host Example

Figure 133. Avalon Bursting Write HostThis example shows the architecture of a bursting write host that receives data from a FIFO and writes the contents to memory. You can use a bursting host as a starting point for your own bursting components, such as custom DMAs, hardware accelerators, or off-chip communication interfaces.


The host performs word accesses and writes to sequential memory locations. When go is asserted, the start_address and transfer_length are registered. On the next clock cycle, the control logic asserts burst_begin, which synchronizes the internal control signals in addition to the host_address and host_burstcount presented to the interconnect. The timing of these two signals is important because during bursting write transfers byteenable and burstcount must be held constant for the entire burst.

To avoid inefficient writes, the host posts a burst when enough data is buffered in the FIFO. To maximize the burst efficiency, the host should stall only when an agent asserts waitrequest. In this example, the FIFO’s used signal tracks the number of words of data that are stored in the FIFO and determines when enough data has been buffered.

The address register increments after every word transfer, and the length register decrements after every word transfer. The address remains constant throughout the burst. Because a transfer is not guaranteed to complete on burst boundaries, additional logic is necessary to recognize the completion of short bursts and complete the transfer.