Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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7.4.1. Avalon® Data Pattern Generator Intel® FPGA IP

The Avalon® Data Pattern Generator IP accepts commands to generate data via an Avalon® memory mapped command interface, and drives the generated data to an Avalon® streaming data interface. You can parameterize most aspects of the Avalon® streaming data interface, such as the number of error bits and data signal width, thus allowing you to test components with different interfaces.

Figure 228.  Avalon® Data Pattern Generator Intel® FPGA IP

The data pattern is calculated as: Symbol Value = Symbol Position in Packet XOR Data Error Mask. Data that is not organized in packets is a single stream with no beginning or end. The Avalon® Data Pattern Generator IP has a throttle register that is set via the Avalon® memory mapped control interface. The Avalon® Data Pattern Generator IP uses the value of the throttle register in conjunction with a pseudo-random number generator to throttle the data generation rate.