Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 9/26/2022
Public

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6.5.1.1.4. HSSI Serial Clock Example

HSSI Serial Clock Interface Example

You can make connections to declare the HSSI Serial Clock interfaces in the _hw.tcl.

package require -exact qsys 14.0

set_module_property name hssi_serial_component
set_module_property ELABORATION_CALLBACK elaborate

add_fileset QUARTUS_SYNTH QUARTUS_SYNTH generate
add_fileset SIM_VERILOG SIM_VERILOG generate
add_fileset SIM_VHDL SIM_VHDL generate

set_fileset_property QUARTUS_SYNTH TOP_LEVEL \
"hssi_serial_component"

set_fileset_property SIM_VERILOG TOP_LEVEL "hssi_serial_component"
set_fileset_property SIM_VHDL TOP_LEVEL "hssi_serial_component"

proc elaborate {} {
	# declaring HSSI Serial Clock Source
	add_interface my_clock_start hssi_serial_clock start
	set_interface_property my_clock_start  ENABLED true

	add_interface_port my_clock_start  hssi_serial_clock_port_out \
 clk Output 1

	# declaring HSSI Serial Clock Sink
	add_interface my_clock_end hssi_serial_clock end
	set_interface_property my_clock_end  ENABLED true

	add_interface_port my_clock_end  hssi_serial_clock_port_in clk \
 Input 1
}

proc generate { output_name } {

	add_fileset_file hssi_serial_component.v VERILOG PATH \
 "hssi_serial_component.v"
}

HSSI Serial Clock Instantiated in a Composed Component

If you use the components in a hierarchy, for example, instantiated in a composed component, you can declare the connections as illustrated in this example.

add_instance myinst1 hssi_serial_component
add_instance myinst2 hssi_serial_component
# add connection from source of myinst1 to sink of myinst2

add_connection myinst1.my_clock_start myinst2.my_clock_end \
hssi_serial_clock

# adding connection from source of myinst2 to sink of myinst1 

add_connection myinst2.my_clock_start myinst2.my_clock_end \
hssi_serial_clock